Emulator

This behavior is mentioned in https://patents.google.com/patent/US6606689:

The data RAM is organized as 4 pages, each page being 1 kword in size. The data ROM is organized as 1 page having a size of 2 kword. One data RAM page is made up of four copies of 256×16-bit synchronous one way dual port SRAM and the data ROM page is made up of a copy of 2048×16-bit synchronous single port ROM. Each page is independent of the other pages so that each page has its own data, address busses and read, write control signals to connect to the three requesters. Data in/out ports for DSP buses 1 and 2 are 16 bits wide and the data in/out ports for DSP DMA 819 are 64 bits. In this arrangement, up to three pages can be active simultaneously for three requesters.
In this example system, each SRAM page can be accessed by one read or one write or one read and one write, but cannot be accessed by two reads or two writes. The reads could be DSP bus 1 or 2 or DSP DMA read and the writes could be DSP bus 1 or 2 or DSP DMA write. The ROM page can only be accessed by one read and the read can be a DSP bus 1 or 2 read. DSP DMA 819 cannot read the data ROM. If a page is being read by DSP DMA, DSP 811 can still write the page or read/write other pages. If a page is being written by DSP DMA 819, DSP 811 can still read the page or read/write other pages. To avoid hardware conflicts, the DSP read and the DMA write or the DSP write and DMA read should not occur on the same address location. DSP 811 is not allowed to read the page that the DMA is reading and the DSP is not allowed to write the page to which the DMA is writing.

Based on that I assume whoever developed the official uCodes knew about this and avoided triggering it. It's still probably worth implementing for accuracy purposes though (at least in the interpreter).

Note that Dolphin does emulate simultaneous writes to an instruction (e.g. INC'L $ac0 : $ac0.l, @$ar0), although this is not enabled by default. See https://github.com/dolphin-emu/dolphin/blob/5674afa63d86308caa5a1a0cbebac7dd3ab031e9/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp#L25-L42.