We only test builds against the versions of our dependencies we pin to in our Externals directory, sorry. We might update at some point, I don't think there's a reason not to. (in fact, if you do want to, please feel free to send a PR to...delroth
> The problem is we take the performance hit on both unaligned aligned uncached writes, we can't tell them apart ahead of time. Can we not slowmem the uncached memory space?delroth
It definitely seems like there's an interaction with either the instruction pipeline, the load/store execution units on the CPU, or something else altogether. So far we've found many ways in which it freezes, one very careful way where i...delroth
Good news: turns out my repro was broken because I accidentally dropped a volatile at a critical place and the compiler decided it should just make all the writes aligned... Bad news: now the repro looks pretty much as simple as it co...delroth
Basic attempts at a repro failed, so it seems like there must be some kind of funny business involved. Here are the cases I've tested, for completeness. ubuffer here is a 16B aligned uncached MEM1 address: ~~~ printf("aligned 32b to...delroth
Has someone managed to reproduce this on real hardware with a minimal test case? e.g. a single "stw" to the uncached 1T-SRAM mapping which triggers the 128B overwrite. This would be a good starting point. #3 mentions trying to reprodu...delroth